Since I released the PLC14500-Nano, I received several questions on the choice of adding a pulse generator to shape the MC14500 W line. I decided to collect here my thoughts on the issue. I hope it can help shed light and, perhaps, help others design a similar system.
The Write line, quite unsurprisingly, plays a role in the execution of STOre instructions. When asserted, this line indicates the MC14500 wants to write the value in RR, available on the D pin, to whichever I/O address is currently selected by the instruction parameter. The principle is simple: drive any output latch so that it stores D when W is asserted.
Let's see in detail how this is implemented on the PLC14500-Nano. Below you can see the program counter is clocked by X1. If we look at the datasheet of the 74HC590A, tying CPC and CPR together causes the output on Q0-Q7 to increase by 1 on each positive edge of the clock. Keep this fact in mind: the address on the A0-A7 lines changes on the positive edge of X1.
Since A0-A7 drive directly the address bus of the program RAM (U8) we can also rephrase this to: the instruction and I/O address change on the positive edge of X1.
Next let's take a look at the output latch configuration. Here we use a CD4099, an addressable 8 bit latch. The most important characteristic of this latch, as far as this discussion is concerned, is the behaviour of the WD line. This is the "Write Disable" line. According to the datasheet, when this line is low the output addressed by A0-A2 follows the D line. When the WD turns high "writing to the output" is disabled and the output latches on whatever state it was on the rising edge of WD.
So, the other summarized fact to keep in mind is: the current value of D is latched on the addressed output on the positive edge of WD.
You might think we just need to negate W and use it directly to drive the CD4099 WD pin. However, if we did this, we would notice certain sequences of instructions to cause unexpected outputs to turn on. I've learned this the hard way on the REV.A of my PLC14500-Nano (an early proto that never made it to the market).
To undestand the issue we need to look at the timing diagram below, which I composed starting from the MC14500 Datasheet, exaggerating certain aspects for clarity.
If we start from T=2, on the rising edge of X1, we see that the advancement of the Program Counter by one step, causes the STO instruction to be presented on the instruction (I0-I3) lines. At the same time, on the I/O address bus, the desired destianation for the STO is set (each program byte low nibble is the instruction and the high nibble the argument, that is the I/O address).
Shortly after the falling edge of X1, the MC14500 asserts the W line. From the discussion above, if we assume the W line is just negated and fed to the WD line of the 4099s, from this moment the outputs will start to follow the D line and will do so until W falls (ie WD raises back to 1).
The critical moment here is at T=8, the following rising edge of X1. As soon as the Progam Counter advances, a new instruction and, most importantly, a new I/O address will be output by the program RAM. The W line though won't fall until shortly after the rising edge of X1. In the diagram below I have exaggerated this time to make things clear, in reality according to the datasheet it's in the order of 220nS at 5V. Long enough for the CD4099 to latch the value on D at the address pointed by the next instruction and not the intended STO instuction. In the diagram, this happens at T=9 when W falls (hence WD of the CD4099 rises in our hypotetical wiring with just a NOT beween W and WD).
So what's the solution? The solution is to condition W into a short pulse instead of a long one lasting until the next rising edge of X1. This can be seen in the timing diagram WP (Write Pulse) line. This is a conditioned version of W. If we drive the WD line of the CD4099 with a negated WP, the latching will happen at T=7, well inside the low phase of X1 when both the instruction and the I/O address are stable.
For this reason on the PLC14500-Nano I have added a pulse generator triggered by the rising edge of W. This takes the form of a 100nF capacitor and 820 Ohm reistor, followed by two Schmitt Trigger NOT gates (see schematic below).
At rest, when W is low, there's no voltage across C15 in virtue of the high impedance of the NOT gate input. This also means U11D input is low, so its output is high and, in turn, U11E output is low. When W rises to high, a current pulse flows through C15 driving U11D input high (and consequently aslo U11E output high). The capactor qickly charges through R59 and, once it reaches the voltage on the W line, current stops flowing through R59 driving the input of U11D low again, even though W is still high. We have in this way generated a pulse, which length depends only on the values of C15/R59 and is triggered by the rising edge of W.
The ouput of U11D, the first stage, could drive directly the WD line of the CD4099 as it's a negative pulse synced with the rising edge of W. In the PLC14500-Nano though, I don't do this but invert the pulse again and use it to drive the glue logic that takes care to address two CD4099s, one for the actual output, one for the Scratch Pad RAM. But that is out of the scope of this post.
It's important that the NOT gates are Schmitt Tirgger type as the voltage on the input of U11D is not digital, but a ramp. The hysteresis helps to keep the edge of the pulse sharp, avoinding the possiblilty of bouncing.
Now, let's see this in action. Imagine we load on the PLC14500-Nano a simple program reading IN1 and outputting to OUT1 such as the one below.
The critical point is the transition from "STO OUT1" to "JMP 0". These instructions are assembled as 0x98 and 0x0C. According to the theory above, if the CD4099 was to be driven directly by the inverted W line, when the JMP instruction is loaded the high nibble will change from "9" to "0" while the W line is still high for roughly 200nS. We can use D4 to prove our theory, because this will flip from 1 to 0. The scope trace below shows exactly this.
The blue trace is the MC14500 W line, while the yellow one is taken directly from line D4 of the program RAM. As you can see D4 transitions to low while W is still falling. If the CD4099 was driven by this signal (inverted), it would latch the value in D in SPR0 (address 0x00) and not OUT1 (0x09) as desired. Of course if "STO OUT1" was followed by a different instruction, with a different parameter, the STO would happen in yet another location.
Let's see now the same D4 line (again yellow) compared to the conditioned Write Pulse (WP) line (blue).
Here the WP pulse is fully inside the high bit of D4 and the instruction change (falling edge of D4) happens long after WP has fallen back (CD4099 WD has risen) and the value has been latched.
Just for the sake of completeness the trace below compares the W line (blue), straight from the MC14500, and the conditioned signal WP (yellow) at the output of the second NOT gate.
The pulse is clearly shorter, as expected. You will also notice the edges are sharper, a testament to the different eras the two chips originate from.
I hope this can help clarifying the W line timing of the MC14500. If you are designing a device using this ICU and your latches are triggered on the edge of a signal you won't need to condition the W line in this way. This was necessary because of the way the CD4099 drives its outputs and latches. It might seem an overcomplication but the CD4099 offers the advantage to be both a decoder and a latch and, given I had already few NOT gates unused on the board, this approach reduced the overall chip count.
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